1. Field of the Invention
The present invention relates to a processor designed to perform a desired operation on parallel readout data from a plurality of source memories, and an art related thereto.
2. Description of the Related Art
FIG. 10 is a block diagram illustrating a prior art processor. As illustrated in FIG. 10, the processor includes a pair of source memories 501, 502, an address-generating unit 503, and an operating unit 504. The operating unit 504 includes a computer (not shown).
The source memories 501, 502 contain data. The address-generating unit 503 generates address signals A1, A2, read enable signals RE1, RE2, and an operation practice enable signal EE.
A pair of registers 601, 602 retains readout data RD1, RD2 from the source memories 501, 502, respectively.
The operating unit 504 performs an operation on candidate operation data D1, D2 that are fed from the resistors 601 and 602, respectively.
The following briefly describes how the data are read out.
As illustrated in FIG. 10, the data are read out as readout data RD1 from the source memory 501 to the register 601 in response to the address signal A1 and the read enable signal RE1.
Meanwhile, the data are read out as readout data RD2 from the source memory 502 to the register 602 in response to the address signal A2 and the read enable signal RE2.
The operating unit 504 operates the candidate operation data D1, D2 in response to the operation practice enable signal EE.
The following describes data readout with reference to a specific example.
FIG. 11 is a descriptive illustration showing different sets of data contained in the source memories 501, 502 of FIG. 10, respectively.
FIG. 12 is a timing diagram describing how the respective sets of data in the source memories 501, 502 of FIG. 10 are read out.
As illustrated in FIG. 11, assume that the source memory 501 includes a series of candidate operation data D1-yielding data at addresses 0-5, while the source memory 502 includes a series of candidate operation data D2-yielding data at addresses 6#-11#.
As illustrated in FIG. 12, at time “t1”, the read enable signals RE1, RE2 are asserted. As a result, data 0, 6# can be read out as readout data RD1, RD2 in parallel with one another from the source memories 501, 502, respectively.
At time “t2”, the operation practice enable signal EE is asserted. As a result, at time “t3”, data 0 and 6# can be entered into the operating unit 504 as candidate operation data D1, D2, respectively.
Similarly, the remaining data 1-5 and the remaining data 7#-11# can be read out.
However, a problem as discussed below arises when either the source memory 501 or the source memory 502 contains the candidate operation data D1-yielding data and the candidate operation data D2-yielding data.
FIG. 13 is a descriptive illustration showing different sets of data contained in the source memory 501 of FIG. 10.
FIG. 14 is a descriptive illustration showing how the different sets of data in the source memory 501 of FIG. 10 are read out.
As illustrated in FIG. 13, assume that the source memory 501 contains a series of the candidate operation data D1-yielding data at addresses 0-5 and a series of the candidate operation data D2-yielding data at addresses 6-11.
In this instance, as illustrated in FIG. 14, the series of data in the source memory 501 at addresses 6-11 is at first transferred to the source memory 502 at addresses 6#-11# through a data-transferring path 505.
In this way, the transferred data and non-transferred data are arranged in a manner as illustrated in FIG. 11. This step must be taken before a desired operation is performed on the data in the source memory 501 at addresses 0-5 and those in the source memory 502 at addresses 6#-11#.
As described above, when either the source memory 501 or the source memory 502 contains both of the candidate operation data D1-yielding data and the candidate operation data D2-yielding data, loads occur to permit one of such data to be transferred to the other source memory.
In particular, such a disadvantage is turned out to be a problem when a situation as described below is present.
A recent system LSI, in particular, a media-processing LSI that handles image data, requires a very high level of performance. Such requirements tend to be more and more stringent every year because of larger-sized images to be handled as well as enlarged and complicated processing systems to be supported.
In order to meet such requirements, efforts have been made to provide enhanced performance to a processor that is designed to practice a desired operation on parallel readout data from a plurality of source memories. More specifically, the processor has computers horizontally aligned with each other in order to parallel-run them. Alternatively, the computers are vertically aligned with each other in order to provide a deep pipeline. By way of a further alternative, the computers are provided with a system-adapted function. Such efforts have brought about great beneficial effects on an increase in computing performance.
By analyzing LSI processing, it has been determined that the above devised use of the computers to cope with pure signal-processing operation enhances the performance of the processor.
As discussed above, the prior art focuses on the computer in order to provide the enhanced performance of the processor.
However, such an increase in computing performance simultaneously renders the previously described data transfer-caused loads noticeable, which has been inconspicuous so far. As a result, the processor sometimes fails to exercise its performance to the greatest extent.
More specifically, as discussed above, when one of the source memories 501, 502 contains the candidate operation data D1-, D2-yielding data, then one of the data must be transferred to the other source memory although the devised use of the computers enhances the computing performance. This causes a problem in that the processor may fail to exercise its performance to the greatest extent.
Another problem is that electric power is required for transferring the data to the other source memory, which is a factor contributing to a failure in power saving.